After the FSBL handoff, the U-Boot loads Linux on the Arm® Cortex-A53 APU. The U-Boot acts as a secondary boot loader. Using JTAG boot mode as described in Boot Sequence for QSPI-Boot Mode Using JTAG.įor more information, see the PMU Firmware Xilinx Wiki. Using FSBL as described in Boot Sequence for QSPI Boot Mode. Using BootROM as described in Boot Sequence for SD-Boot. The PMU firmware can be loaded in the following ways:
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For more details on the platform management and PMU firmware, see the Zynq UltraScale+ MPSoC: Software Developers Guide ( UG1137). The Vitis IDE provides PMU firmware that can be built to run on the PMU. The PMU handles all of the processes related to reset and wake-up. The PMU primarily controls the pre-configuration stage that executes the PMU ROM to set up the system. The platform management unit (PMU) and the configuration security unit manage and perform the multi-staged booting process. Platform Management Unit Firmware (PMUFW) ¶ When the DDR initialization is completed in FSBL, the memory attributes for the DDR region are changed to “memory” so that they are cacheable. This is to avoid speculative access to DDR memory controller before it is initialized. In the FSBL application, the xfsbl_translation_table.S differs from the translation_table.S of the Cortex-A53 in only one aspect, to mark the DDR region as reserved. For more information, see the Zynq UltraScale+ MPSoC: Software Developers Guideįor this chapter, you can use the FSBL executable that you created in Building Software for PS
In this example, the FSBL loads a bare-metal application in DDR and hands off to the RPU Cortex-R5F in lockstep mode, and then loads U-Boot to be executed by the APU Cortex-A53 Core-0. This includes clearing the reset of the processors and initializing clocks, memory, UART, and so on before handing over the control of the next partition in DDR, to either the RPU or APU. The first stage boot loader initializes important blocks in the processing subsystem. The last 512 bytes of this region are used by FSBL to share the hand-off parameters corresponding to the applications handed off by the TF-A. In this example, the FSBL is targeted for APU Cortex™-A53 Core 0. The FSBL can be run from either APU A53_0, RPU R5_0, or RPU R5_lockstep. At this stage, the configuration security unit loads the first stage boot loader (FSBL) into on-chip memory (OCM). In non-secure boot mode, the platform management unit (PMU) releases the reset of the configuration security unit, and enters the PMU server mode to monitor power. For detailed boot flow and various boot sequences, refer to the System Boot and Configuration chapter in the Zynq UltraScale+ MPSoC: Software Developers Guide The following system software blocks cover most of the boot and configuration for this chapter. Design Example 1: Using GPIOs, Timers, and Interrupts covers the boot image which will include the PS partitions used in this chapter and a bitstream targeted for the PL fabric. This chapter makes use of a processing system block. The Bootgen GUI facilitates the creation of the BIF input file. It can be used to program non-volatile memories such as QSPI and SD cards. It can also create cryptographic keys.įunctionally, Bootgen uses a BIF (Bootgen image format) file as an input, and generates a single file image in binary BIN or MCS format. It allows you to specify security options. The principle function of the Create Boot Image wizard or Bootgen is to integrate the partitions (hardware-bitstream and software) in the proper format. To create a boot image, you can either use the Create Boot Image wizard in the Vitis IDE, or the Bootgen command line tool (the Create Boot Image wizard calls the Bootgen tool as well).
While previous sections focused only on creating software blocks for each processing unit in the PS, this chapter explains how these blocks can be loaded as a part of a bigger system.
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